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| author | Kangheui Won <khwon@chromium.org> | 2021-10-18 15:35:28 +1100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-02 08:17:32 +0000 |
| commit | fab6e44a95e8217818254d69de4ba648bfa9e8ed (patch) | |
| tree | 1248e73764761e8020971ce4720e8e85ca0b76bd /src/soc/amd/cezanne/include/soc/iomap.h | |
| parent | cb3745c407f0c19bfcab06b05549ad20948efff9 (diff) | |
| download | coreboot-fab6e44a95e8217818254d69de4ba648bfa9e8ed.tar.gz coreboot-fab6e44a95e8217818254d69de4ba648bfa9e8ed.tar.bz2 coreboot-fab6e44a95e8217818254d69de4ba648bfa9e8ed.zip | |
psp_verstage: convert relative address in EFS2
Addresses in AMD fw table with EFS gen2 are relative addresses, but
PSP doesn't accept relative addresses in update_psp_bios_dir().
Check for EFS gen2 and convert them as needed.
BUG=b:194263115
TEST=build and boot on guybrush and shuboz
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I95813beba7278480e6640599fcf7445923259361
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/cezanne/include/soc/iomap.h')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/iomap.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index a4f0f30d8041..f83f13aa2da4 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -36,10 +36,10 @@ #define APU_EMMC_BASE 0xfedd5000 #define APU_EMMC_CONFIG_BASE 0xfedd5800 -#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) - #endif /* ENV_X86 */ +#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) + /* I/O Ranges */ #define ACPI_IO_BASE 0x0400 #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) |