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| author | Kangheui Won <khwon@chromium.org> | 2021-03-23 14:56:31 +1100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-03-24 19:37:09 +0000 |
| commit | 39ef89033624a2d14b0c77cdbdf287dd7d7059e1 (patch) | |
| tree | cfd0cf17f5f835e7af14a85539f1fcf3ab4ce506 /src/soc/amd/cezanne/include/soc/southbridge.h | |
| parent | 6d837df90838bfb3a9c877b5c0b2eeda85e3d9f0 (diff) | |
| download | coreboot-39ef89033624a2d14b0c77cdbdf287dd7d7059e1.tar.gz coreboot-39ef89033624a2d14b0c77cdbdf287dd7d7059e1.tar.bz2 coreboot-39ef89033624a2d14b0c77cdbdf287dd7d7059e1.zip | |
mb/google/guybrush: disable KBRSTEN
GPIO129 is muxed with KBRST, so setting GPIO129 to low causes reset
when KBRSTEN is set to 1. Since reset value of KBRSTEN is 1 we need a
logic to clear it.
BUG=b:183340503
TEST=build
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I194e8432a14d6105f6bcf12111647f5aad4e2de2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/include/soc/southbridge.h')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/southbridge.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 05dd9b36e3c5..de96355942ee 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -54,6 +54,7 @@ #define PM_ACPI_RTC_WAKE_EN BIT(29) #define PM_RST_CTRL1 0xbe #define SLPTYPE_CONTROL_EN BIT(5) +#define KBRSTEN BIT(4) #define PM_LPC_GATING 0xec #define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_A20_EN BIT(1) |