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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-09 02:01:16 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-11 17:44:42 +0000 |
| commit | 44f41537af4022ce8d8c4fadb6b690b3ec6f8c61 (patch) | |
| tree | d28b4299b86f996f768f723c2a844a0146c3c606 /src/soc/amd/cezanne/include/soc/southbridge.h | |
| parent | e04a18fc25cfb28690cd7dbd3302a63436b1ccd2 (diff) | |
| download | coreboot-44f41537af4022ce8d8c4fadb6b690b3ec6f8c61.tar.gz coreboot-44f41537af4022ce8d8c4fadb6b690b3ec6f8c61.tar.bz2 coreboot-44f41537af4022ce8d8c4fadb6b690b3ec6f8c61.zip | |
soc/amd/cezanne: add 0xcf9 reset
Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/include/soc/southbridge.h')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/southbridge.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 2456ebc6f99c..03ee2bb2d194 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -5,6 +5,13 @@ #include <soc/iomap.h> +/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ +#define PWR_RESET_CFG 0x10 +#define TOGGLE_ALL_PWR_GOOD (1 << 1) + +/* IO 0xf0 NCP Error */ +#define NCP_WARM_BOOT (1 << 7) /* Write-once */ + void fch_pre_init(void); void fch_early_init(void); |