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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-05-28 19:42:57 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-06-11 21:48:28 +0000 |
| commit | c0fd6e5ea643557254a23a7aa7b7b98f64d18737 (patch) | |
| tree | bd50fdd2d40b904bac1f97dc75280b40f5f1c16a /src/soc/amd/cezanne/include/soc/southbridge.h | |
| parent | dee3bc34ad3be944390369724a46ecf01398c51a (diff) | |
| download | coreboot-c0fd6e5ea643557254a23a7aa7b7b98f64d18737.tar.gz coreboot-c0fd6e5ea643557254a23a7aa7b7b98f64d18737.tar.bz2 coreboot-c0fd6e5ea643557254a23a7aa7b7b98f64d18737.zip | |
soc/amd/cezanne: remove warm reset flag code
The warm reset bit in the NCP_ERR register doesn't behave as the PPR [1]
suggested; no matter if something was written to the register, the
NCP_WARM_BOOT bit never got set and the NCP_ERR register in I/O-space
always reads back as 0x7f.
[1] checked with PPR for AMD Family 19h Model 51h A1 (CZN) #56569 Rev
3.01
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I569372db9f36ec7bbc741f4d7312ade312daa70b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55101
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/include/soc/southbridge.h')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/southbridge.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index e58a8cd2ca8c..e82f33f9c8be 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -118,9 +118,6 @@ #define FCH_AOAC_DEV_AMBA 17 #define FCH_AOAC_DEV_ESPI 27 -/* IO 0xf0 NCP Error */ -#define NCP_WARM_BOOT (1 << 7) /* Write-once */ - void fch_pre_init(void); void fch_early_init(void); void fch_init(void *chip_info); |