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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-03-25 00:50:34 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-03-29 18:56:36 +0000 |
| commit | c1042ba2c5dc19194a75a87f1e717f411582dc9a (patch) | |
| tree | 6ac2cc28df5261e293fe1252a3627ca5a9747534 /src/soc/amd/cezanne/include/soc/southbridge.h | |
| parent | 51d6f5cc0a75c32a19489fb22f004b4678bbd9f4 (diff) | |
| download | coreboot-c1042ba2c5dc19194a75a87f1e717f411582dc9a.tar.gz coreboot-c1042ba2c5dc19194a75a87f1e717f411582dc9a.tar.bz2 coreboot-c1042ba2c5dc19194a75a87f1e717f411582dc9a.zip | |
soc/amd: move PM_RST_CTRL1 register definition to common acpimmio header
TEST=Verified that this register and the defined bits exist in Cezanne,
Picasso, Stoneyridge, Bolton and SB800.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I32d1d577b05edab006981516a5aefd822e7b984a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/cezanne/include/soc/southbridge.h')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/southbridge.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index de96355942ee..157ad4ec3ccc 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -52,9 +52,6 @@ #define PM_ACPI_WAKE_AS_GEVENT BIT(27) #define PM_ACPI_NB_PME_GEVENT BIT(28) #define PM_ACPI_RTC_WAKE_EN BIT(29) -#define PM_RST_CTRL1 0xbe -#define SLPTYPE_CONTROL_EN BIT(5) -#define KBRSTEN BIT(4) #define PM_LPC_GATING 0xec #define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_A20_EN BIT(1) |