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| author | Martin Roth <martinroth@chromium.org> | 2021-06-21 09:22:13 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-06-23 19:01:16 +0000 |
| commit | 6662fe60e1022e293519d098af8c22001991e9b4 (patch) | |
| tree | ec3be43ad6e64c158394bd2a4822ffaddf4c5fda /src/soc/amd/cezanne/include | |
| parent | 7c21c208217705c4dbcb3db8e92891229efb2bda (diff) | |
| download | coreboot-6662fe60e1022e293519d098af8c22001991e9b4.tar.gz coreboot-6662fe60e1022e293519d098af8c22001991e9b4.tar.bz2 coreboot-6662fe60e1022e293519d098af8c22001991e9b4.zip | |
soc/amd/cezanne: Init eSPI early if required
If the NO_EARLY_BOOTBLOCK_POSTCODES config option is enabled, configure
eSPI as early as possible in the x86 boot sequence.
We found that there are situations that can cause the system to hang if
there are any port80h postcodes sent out before eSPI is initialized.
BUG=b:191370340
TEST=Build & Boot with and without NO_EARLY_BOOTBLOCK_POSTCODES enabled.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0badb1c529e96ee4f81134287db53ce32473de6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55732
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/include')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/southbridge.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 0ed5f33f22ae..386d3c1e879f 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -105,6 +105,7 @@ #define I2C_PAD_CTRL_SPARE0 BIT(17) #define I2C_PAD_CTRL_SPARE1 BIT(18) +void configure_port80_routing_early(void); void fch_pre_init(void); void fch_early_init(void); void fch_init(void *chip_info); |