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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-04-12 23:44:14 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-14 00:00:27 +0000 |
| commit | 0d2c0019e284aea3b1889579782495afb6e52daf (patch) | |
| tree | ac8a6a574b8f4be3f8264b5d3e2466b27eddc249 /src/soc/amd/cezanne/romstage.c | |
| parent | 651d5214d25641052a757e3f6eec75e4a1af9f9c (diff) | |
| download | coreboot-0d2c0019e284aea3b1889579782495afb6e52daf.tar.gz coreboot-0d2c0019e284aea3b1889579782495afb6e52daf.tar.bz2 coreboot-0d2c0019e284aea3b1889579782495afb6e52daf.zip | |
soc/amd/picasso/romstage: factor out chipset state saving functionality
Since Cezanne needs the exact same code, move it to the common directory
and add a Kconfig option to add this functionality to the build.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I04c4295071a3df7afcb4dfd5435b11fb0bf6963f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/romstage.c')
0 files changed, 0 insertions, 0 deletions