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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-03-03 20:54:38 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-09 19:01:15 +0000 |
| commit | 697fa74027402e8eb01c69ee6407599f6cacca75 (patch) | |
| tree | 6d6d09d51c49b2179b737ad930987408356bdba2 /src/soc/amd/cezanne | |
| parent | 6f73a202d3df000fb2fd83080e0b148add344485 (diff) | |
| download | coreboot-697fa74027402e8eb01c69ee6407599f6cacca75.tar.gz coreboot-697fa74027402e8eb01c69ee6407599f6cacca75.tar.bz2 coreboot-697fa74027402e8eb01c69ee6407599f6cacca75.zip | |
soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTER
Rename SPIROM_BASE_ADDRESS_REGISTER to SPI_BASE_ADDRESS_REGISTER to
clarify that this isn't the address the SPI flash gets mapped, but the
address of the SPI controller MMIO region. This also aligns the register
name with the PPR.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/lpc.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/include/soc/lpc.h b/src/soc/amd/cezanne/include/soc/lpc.h index 123a13fc8919..084159e561df 100644 --- a/src/soc/amd/cezanne/include/soc/lpc.h +++ b/src/soc/amd/cezanne/include/soc/lpc.h @@ -9,7 +9,7 @@ #define LPC_LDRQ0_PU_EN BIT(10) #define LPC_LDRQ0_PD_EN BIT(9) -#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ADDRESS_REGISTER 0xa0 #define SPI_BASE_ALIGNMENT BIT(8) #define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7)) #define PSP_SPI_MMIO_SEL BIT(4) |