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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-06-23 11:53:34 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-14 23:10:17 +0000 |
| commit | 84b2f9f5b8e40eb9a114c1be5741b4141c5566e0 (patch) | |
| tree | 6d7eff7f689cb392db7ee8401f9626905a1151cf /src/soc/amd/cezanne | |
| parent | b95a821576d0a1923e6a115b0d8272cd25890bfe (diff) | |
| download | coreboot-84b2f9f5b8e40eb9a114c1be5741b4141c5566e0.tar.gz coreboot-84b2f9f5b8e40eb9a114c1be5741b4141c5566e0.tar.bz2 coreboot-84b2f9f5b8e40eb9a114c1be5741b4141c5566e0.zip | |
lib/program_loaders.c: Mark run_ramstage with __noreturn
This allows the compiler to optimize out code called after run_ramstage.
Also remove some die() statements in soc code as run_ramstage already
has a die_with_postcode statement.
Change-Id: Id8b841712661d3257b0dc67b509f97bdc31fcf6f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/romstage.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index 7a395bdf9b2d..dce0b697357a 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -25,5 +25,4 @@ void __noreturn romstage_main(void) memmap_stash_early_dram_usage(); run_ramstage(); - die("failed to load ramstage\n"); } |