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| author | Fred Reitberger <reitbergerfred@gmail.com> | 2022-04-12 13:44:34 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-07 12:47:40 +0000 |
| commit | 96f7b96866b0bce7a1323c4da478f838f884383f (patch) | |
| tree | 14aacbd95bf6c5b76a620b15eded0b3ad018f9fb /src/soc/amd/cezanne | |
| parent | 749f5bd333e34a61d1ea09d8f3b2fd8feb172f6b (diff) | |
| download | coreboot-96f7b96866b0bce7a1323c4da478f838f884383f.tar.gz coreboot-96f7b96866b0bce7a1323c4da478f838f884383f.tar.bz2 coreboot-96f7b96866b0bce7a1323c4da478f838f884383f.zip | |
soc/amd/common/block/cpu/: Make ucode update more generic
Use the equivalent cpuid in the microcode header to name the update file
in cbfs. This allows the SOC to directly locate its microcode file when
there are multiple processor revisions.
TEST: Loaded a chausie with sabrina, cezanne, and picasso microcode
files and booted. Verified that only the sabrina microcode file was
successfully loaded
Change-Id: I84a2480cf8274d53ffdab7864135c1bf001241e6
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 302deaa4ce61..c46c577e8929 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -300,6 +300,6 @@ apu/amdfw_b-position := $(AMD_FW_AB_POSITION) apu/amdfw_b-type := raw endif -cpu_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/UcodePatch_*.bin) +amd_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/UcodePatch_*.bin) endif # ($(CONFIG_SOC_AMD_CEZANNE),y) |