diff options
| author | Tim Van Patten <timvp@google.com> | 2022-09-13 15:34:08 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-15 17:58:31 +0000 |
| commit | 9eac09720555f22cf5374665e395525c7afa218e (patch) | |
| tree | 1f3fb593ccb3021888e9a8ad5aeea62b681e3963 /src/soc/amd/cezanne | |
| parent | 54ce4aa98cf55f0715670be4f592a39adcf82328 (diff) | |
| download | coreboot-9eac09720555f22cf5374665e395525c7afa218e.tar.gz coreboot-9eac09720555f22cf5374665e395525c7afa218e.tar.bz2 coreboot-9eac09720555f22cf5374665e395525c7afa218e.zip | |
amd/cezanne: Control DPTC with only Kconfig
SOC_AMD_COMMON_BLOCK_ACPI_DPTC can be enabled conditionally for any
guybrush boards, similar to .mainboard/google/zork/Kconfig This makes
the value dptc_tablet_mode_enable redundant.
This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely
with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC
is only included for boards that actually enable it.
BRANCH=none
BUG=b:217911928
TEST=emerge-guybrush coreboot
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I07f1266fa80a6c9ee4ec3b3ba970a70c6c72fb54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/root_complex.c | 8 |
2 files changed, 3 insertions, 7 deletions
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index b22590a02182..00eb560b646c 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -86,8 +86,6 @@ struct soc_amd_cezanne_config { uint32_t telemetry_vddcrsocfull_scale_current_mA; uint32_t telemetry_vddcrsocoffset; - bool dptc_enable; - /* The array index is the general purpose PCIe clock output number. Values in here aren't the values written to the register to have the default to be always on. */ enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 77a94f52d7a2..8ea5c9fb2957 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -186,10 +186,7 @@ static void acipgen_dptci(void) { const struct soc_amd_cezanne_config *config = config_of_soc(); - if (!config->dptc_enable) - return; - - /* DPTC is enabled. Always fill out the default DPTC values. */ + /* Normal mode DPTC values. */ struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC, config->sustained_power_limit_mW, config->fast_ppt_limit_mW, @@ -200,7 +197,8 @@ static void acipgen_dptci(void) static void root_complex_fill_ssdt(const struct device *device) { acpi_fill_root_complex_tom(device); - acipgen_dptci(); + if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)) + acipgen_dptci(); } static const char *gnb_acpi_name(const struct device *dev) |