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authorRaul E Rangel <rrangel@chromium.org>2022-02-25 12:40:32 -0700
committerKarthik Ramasubramanian <kramasub@google.com>2022-03-10 17:06:51 +0000
commite6cd6caf31d1e22b56a94c941f50b47e77bb41cd (patch)
treeaa096036aa8978a806f18b02a1b78db73a018f28 /src/soc/amd/cezanne
parent496734379dc0e6873a2d81edf0872987be5be4c0 (diff)
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cpu/x86/smm: Add weak SoC init and exit methods
This change provides hooks for the SoC so it can perform any initialization and cleanup in the SMM handler. For example, if we have a UART enabled firmware with DEBUG_SMI, the UART controller could have been powered off by the OS. In this case we need to power on the UART when entering SMM, and then power it off before we exit. If the OS had the UART enabled when entering SMM, we should snapshot the UART register state, and restore it on exit. Otherwise we risk clearing some interrupt enable bits. BUG=b:221231786, b:217968734 TEST=Build test guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I946619cd62a974a98c575a92943b43ea639fc329 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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