soc/amd/common: Add AcpiMmio access for SMBus PCI device

The standard PCI register space for D14F0 is accessible at 0xfed80000.
Add functions for use as helpers.

Change-Id: Icbf5bdc449322c3f5e59e6126d709cb2808591d5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 33 insertions, 1 deletions

diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c
index edb3882e6fc4..7fad45610678 100644
--- a/src/soc/amd/common/block/acpimmio/mmio_util.c
+++ b/src/soc/amd/common/block/acpimmio/mmio_util.c
@@ -65,7 +65,39 @@ void pm_io_write32(uint8_t reg, uint32_t value)
 	pm_io_write16(reg + sizeof(uint16_t), value & 0xffff);
 }
 
-/* smbus pci read/write - access registers at 0xfed80000 - currently unused */
+#if SUPPORTS_ACPIMMIO_SM_PCI_BASE
+/* smbus pci read/write - access registers at 0xfed80000 */
+
+u8 sm_pci_read8(u8 reg)
+{
+	return read8((void *)(ACPIMMIO_SM_PCI_BASE + reg));
+}
+
+u16 sm_pci_read16(u8 reg)
+{
+	return read16((void *)(ACPIMMIO_SM_PCI_BASE + reg));
+}
+
+u32 sm_pci_read32(u8 reg)
+{
+	return read32((void *)(ACPIMMIO_SM_PCI_BASE + reg));
+}
+
+void sm_pci_write8(u8 reg, u8 value)
+{
+	write8((void *)(ACPIMMIO_SM_PCI_BASE + reg), value);
+}
+
+void sm_pci_write16(u8 reg, u16 value)
+{
+	write16((void *)(ACPIMMIO_SM_PCI_BASE + reg), value);
+}
+
+void sm_pci_write32(u8 reg, u32 value)
+{
+	write32((void *)(ACPIMMIO_SM_PCI_BASE + reg), value);
+}
+#endif
 
 #if SUPPORTS_ACPIMMIO_SMI_BASE
 /* smi read/write - access registers at 0xfed80200 */