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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-07-03 00:24:28 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-08 16:47:27 +0000 |
| commit | de7262f82cdc1a7c868dbc9ca41e186e885eb2ba (patch) | |
| tree | e8fe2e84070eb60d8baeeea7e0a2e17c8c4dfba3 /src/soc/amd/common/block/gpio_banks | |
| parent | f8e440cadf4f332c676fddafd0357ecc07de5a4c (diff) | |
| download | coreboot-de7262f82cdc1a7c868dbc9ca41e186e885eb2ba.tar.gz coreboot-de7262f82cdc1a7c868dbc9ca41e186e885eb2ba.tar.bz2 coreboot-de7262f82cdc1a7c868dbc9ca41e186e885eb2ba.zip | |
soc/amd: remove special GPIO_2 override soc_gpio_hook
This override was added to have the SCI mapping configured if GPIO was
used as WAKE_L pin. This however didn't set up the SCI level and trigger
information, so it likely never worked as intended.
Change-Id: I44661f05c8f517ece88714c625603579731d174b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/common/block/gpio_banks')
| -rw-r--r-- | src/soc/amd/common/block/gpio_banks/gpio.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index af948ce35749..186df5093d46 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -179,8 +179,6 @@ uint16_t gpio_acpi_pin(gpio_t gpio) return gpio; } -__weak void soc_gpio_hook(uint8_t gpio, uint8_t mux) {} - static void set_single_gpio(const struct soc_amd_gpio *g, struct sci_trigger_regs *sci_trigger_cfg) { @@ -193,8 +191,6 @@ static void set_single_gpio(const struct soc_amd_gpio *g, iomux_write8(g->gpio, g->function & AMD_GPIO_MUX_MASK); iomux_read8(g->gpio); /* Flush posted write */ - soc_gpio_hook(g->gpio, g->function); - gpio_setbits32(g->gpio, PAD_CFG_MASK, g->control); /* Clear interrupt and wake status (write 1-to-clear bits) */ gpio_or32(g->gpio, GPIO_INT_STATUS | GPIO_WAKE_STATUS); |