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| author | Varshit Pandya <pandyavarshit@gmail.com> | 2024-02-08 21:32:57 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-10 16:53:22 +0000 |
| commit | 0452d0939e7d7ddbf24d78ad5e69408b5ad52f47 (patch) | |
| tree | ef428728d58e7e955bc26cc909380a45c5a37194 /src/soc/amd/common/block/gpp_clk/Kconfig | |
| parent | 9f297080aa1ec6b45551f7a177a21394e627c3e2 (diff) | |
| download | coreboot-0452d0939e7d7ddbf24d78ad5e69408b5ad52f47.tar.gz coreboot-0452d0939e7d7ddbf24d78ad5e69408b5ad52f47.tar.bz2 coreboot-0452d0939e7d7ddbf24d78ad5e69408b5ad52f47.zip | |
soc/amd: Factor out gpp_clk_setup function
gpp_clk_setup code in most AMD SoC is similar and it can moved to common
code. The only thing which is SoC dependent in this function is the SoC
config, hence keep it in SoC code and move everything else in new
gpp_clk_setup_common function which is in soc/amd/common. Picasso and
Glinda don't have pcie_gpp_dxio_update_clk_req_config fixup function so
they are addressed in later patches.
Change-Id: I7d7da4bfe079f07e31212247dbf3acd14daa6447
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80285
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/common/block/gpp_clk/Kconfig')
| -rw-r--r-- | src/soc/amd/common/block/gpp_clk/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/gpp_clk/Kconfig b/src/soc/amd/common/block/gpp_clk/Kconfig new file mode 100644 index 000000000000..0838df41d43f --- /dev/null +++ b/src/soc/amd/common/block/gpp_clk/Kconfig @@ -0,0 +1,4 @@ +config SOC_AMD_COMMON_BLOCK_GPP_CLK + bool + help + Select this option to use AMD common PCIe clk generator configuration. |