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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-06-06 00:29:58 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-07 00:05:30 +0000 |
| commit | 11ff753407ee7fd1cb2da06f8bedc5ac40ebbd95 (patch) | |
| tree | 6ecbb219bf48422b94a9e6ccdc89ba87a9a1bf16 /src/soc/amd/common/block/include/amdblocks | |
| parent | b39e93e56fdd2b11b8e7a12889472f144673d05a (diff) | |
| download | coreboot-11ff753407ee7fd1cb2da06f8bedc5ac40ebbd95.tar.gz coreboot-11ff753407ee7fd1cb2da06f8bedc5ac40ebbd95.tar.bz2 coreboot-11ff753407ee7fd1cb2da06f8bedc5ac40ebbd95.zip | |
soc/amd/common/block/cpu/noncar: add get_usable_physical_address_bits()
In case the secure memory encryption is enabled, some of the upper
usable address bits of the host can't be used any more. Bits 11..6 in
CPUID_EBX_MEM_ENCRYPT indicate how many of the address bits are taken
away from the usable address bits in the case the secure memory
encryption is enabled.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia810b0984972216095da2ad8f9c19e37684f2a2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75623
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/common/block/include/amdblocks')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h index 4aa225bda36f..10dd23f11b7c 100644 --- a/src/soc/amd/common/block/include/amdblocks/cpu.h +++ b/src/soc/amd/common/block/include/amdblocks/cpu.h @@ -12,6 +12,7 @@ void early_cache_setup(void); int get_cpu_count(void); unsigned int get_threads_per_core(void); void set_cstate_io_addr(void); +uint32_t get_usable_physical_address_bits(void); void write_resume_eip(void); union pstate_msr; /* proper definition is in soc/msr.h */ |