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authorKarthikeyan Ramasubramanian <kramasub@google.com>2023-10-16 21:08:57 +0000
committerMatt DeVillier <matt.devillier@amd.corp-partner.google.com>2023-10-20 14:26:25 +0000
commit204a4e6d9f2712dc9f78d44bb9820a7ab859f5d0 (patch)
treee3d9d789b3781a0626b188c2b0ac7b7e20efc3cf /src/soc/amd/common/psp_verstage/Kconfig
parent64ba070fd164fc307fe02051e8480db573fc1ac6 (diff)
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soc/amd/common/psp_verstage: Add PSP_VERSTACK_STACK_IS_MAPPED config
Crypto Engine in PSP prefers the buffer from Static RAM (SRAM). Hence if a buffer comes from within SRAM address range, then it is passed directly to Crypto Engine. Otherwise a bounce bufer from the stack is used. But on SoCs like Picasso where PSP Verstage stack is mapped to a virtual address space this check fails causing a bounce buffer to be used and hence a stack overflow. Fix this issue by assuming that the buffer comes from the SRAM always in such SoCs and pass the buffer directly to crypto engine. BUG=b:259649666 TEST=Build and boot to OS in Dalboz with unsigned PSP verstage. Change-Id: I2161c8f0720c770efa5c05aece9584c3cbe7712a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/common/psp_verstage/Kconfig')
-rw-r--r--src/soc/amd/common/psp_verstage/Kconfig8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/amd/common/psp_verstage/Kconfig b/src/soc/amd/common/psp_verstage/Kconfig
index 526a4ae722e6..dc6ea1c3eeb5 100644
--- a/src/soc/amd/common/psp_verstage/Kconfig
+++ b/src/soc/amd/common/psp_verstage/Kconfig
@@ -35,3 +35,11 @@ config SEPARATE_SIGNED_PSPFW
help
Put signed AMD/PSP firmwares outside FW_MAIN_[AB] so vboot doesn't verify them,
and rely on PSP's verification.
+
+config PSP_VERSTAGE_STACK_IS_MAPPED
+ bool
+ default y if SOC_AMD_PICASSO
+ default n
+ help
+ This configuration indicates whether the PSP Verstage stack is mapped to a virtual
+ address space. This has been the case so far only in Picasso SoC.