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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-01-11 16:20:32 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-25 03:18:58 +0000 |
| commit | 421c7d1a9904f1f74d017c053da9cc4a4e1586aa (patch) | |
| tree | a35e03564dbd3c0c8f4da55eca5df4f326d38804 /src/soc/amd/common | |
| parent | 3c44c6227e5170d1d631f88fb3980b5f18cd75b9 (diff) | |
| download | coreboot-421c7d1a9904f1f74d017c053da9cc4a4e1586aa.tar.gz coreboot-421c7d1a9904f1f74d017c053da9cc4a4e1586aa.tar.bz2 coreboot-421c7d1a9904f1f74d017c053da9cc4a4e1586aa.zip | |
soc/amd/common/block/include/psp_efs: update defines for sabrina
Document #55758 Rev. 1.13 says that family 17h models 30h-3Fh and later
use the spi_readmode_f17_mod_30_3f struct element for SPI_MODE_FIELD and
spi_fastspeed_f17_mod_30_3f for SPI_SPEED_FIELD, so also use this for
The AMD Sabrina SoC which is family 17h models A0h-AFh.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I336f9ea4a0defdf34e1af4b6d568cfe46488f75e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/common')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/psp_efs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h index a3996cbf3b7d..af447655193c 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h +++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h @@ -16,7 +16,7 @@ #elif CONFIG(SOC_AMD_PICASSO) #define SPI_MODE_FIELD spi_readmode_f17_mod_00_2f #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_00_2f -#elif CONFIG(SOC_AMD_CEZANNE) +#elif CONFIG(SOC_AMD_CEZANNE) | CONFIG(SOC_AMD_SABRINA) #define SPI_MODE_FIELD spi_readmode_f17_mod_30_3f #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_30_3f #else |