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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-05-14 13:19:43 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-05-16 07:05:03 +0000 |
| commit | 46b409da483ebfc8d9c868c713f5ad68b62c808e (patch) | |
| tree | f6fd02685ea558df7447dc3449d3fba787c09183 /src/soc/amd/common | |
| parent | 645dde77940d12979166555b17dbc81cda1bc48b (diff) | |
| download | coreboot-46b409da483ebfc8d9c868c713f5ad68b62c808e.tar.gz coreboot-46b409da483ebfc8d9c868c713f5ad68b62c808e.tar.bz2 coreboot-46b409da483ebfc8d9c868c713f5ad68b62c808e.zip | |
arch/x86/postcar: Set up postcar MTRR in C code
Setting up postcar MTRRs is done when invd is already called so there
is no reason to do this in assembly anymore.
This also drops the custom code for Quark to set up MTRRs.
TESTED on foxconn/g41m and hermes/prodrive that MTRR are properly set
in postcar & ramstage.
Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54299
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/common')
| -rw-r--r-- | src/soc/amd/common/block/cpu/noncar/early_cache.c | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/src/soc/amd/common/block/cpu/noncar/early_cache.c b/src/soc/amd/common/block/cpu/noncar/early_cache.c index b9650a96a72c..94c8b10272ae 100644 --- a/src/soc/amd/common/block/cpu/noncar/early_cache.c +++ b/src/soc/amd/common/block/cpu/noncar/early_cache.c @@ -1,11 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/cpu.h> +#include <assert.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <soc/iomap.h> +#include <stdint.h> + +/* Allocate a static amount of stack for the MTRR context. */ +#define MAX_VAR_MTRR_USE 10 /* * PSP performs the memory training and setting up DRAM map prior to x86 cores being released. @@ -19,9 +24,15 @@ void early_cache_setup(void) msr_t mtrr_def_type; msr_t fixed_mtrr_ram; msr_t fixed_mtrr_mmio; - struct var_mtrr_context mtrr_ctx; + union mtrr_ctx { + struct var_mtrr_context ctx; + char buffer[sizeof(struct var_mtrr_context) + + 2 * MAX_VAR_MTRR_USE * sizeof(msr_t)]; + + } mtrr_ctx; - var_mtrr_context_init(&mtrr_ctx, NULL); + var_mtrr_context_init(&mtrr_ctx.ctx); + mtrr_ctx.ctx.max_var_mtrrs = MIN(MAX_VAR_MTRR_USE, mtrr_ctx.ctx.max_var_mtrrs); top_mem = rdmsr(TOP_MEM); /* Enable RdDram and WrDram attributes in fixed MTRRs. */ sys_cfg = rdmsr(SYSCFG_MSR); @@ -49,11 +60,11 @@ void early_cache_setup(void) wrmsr(SYSCFG_MSR, sys_cfg); - clear_all_var_mtrr(); - - var_mtrr_set(&mtrr_ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK); + var_mtrr_set(&mtrr_ctx.ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK); /* TODO: check if we should always mark 16 MByte below 4 GByte as WRPROT */ - var_mtrr_set(&mtrr_ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + var_mtrr_set(&mtrr_ctx.ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + commit_mtrr_setup(&mtrr_ctx.ctx); /* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */ wrmsr(MTRR_FIX_64K_00000, fixed_mtrr_ram); |