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| author | Raul E Rangel <rrangel@chromium.org> | 2022-04-28 16:15:03 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-02 14:04:02 +0000 |
| commit | 471f2eefddaa715b9765b7572133c4dde3a25b0c (patch) | |
| tree | 85a280ba3ba6afd686b555d80bb9c30693d8ebf5 /src/soc/amd/common | |
| parent | 6b36dd644c6a2cbc75d487afc7dd56322bb7ec96 (diff) | |
| download | coreboot-471f2eefddaa715b9765b7572133c4dde3a25b0c.tar.gz coreboot-471f2eefddaa715b9765b7572133c4dde3a25b0c.tar.bz2 coreboot-471f2eefddaa715b9765b7572133c4dde3a25b0c.zip | |
soc/amd/common/block/spi: Pretty print SPI status
I find it difficult to constantly decode the registers when reading
them. Let's print out something that's easier to parse.
BUG=b:228289365
TEST=boot guybrush and see status codes printed
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6c9d98cf43f340cf50e12c93b4c35187de9bb750
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/common')
| -rw-r--r-- | src/soc/amd/common/block/spi/fch_spi_ctrl.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index e8f20f3bc6ba..519503dc6d9f 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -39,6 +39,7 @@ static void dump_state(enum spi_dump_state_phase phase) { u8 dump_size; uintptr_t addr; + u32 status; if (!CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)) return; @@ -55,7 +56,17 @@ static void dump_state(enum spi_dump_state_phase phase) } printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0)); - printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS)); + + status = spi_read32(SPI_STATUS); + printk(BIOS_DEBUG, "Status: %x\n", status); + printk(BIOS_DEBUG, + " Busy: %u, FIFO Read Pointer: %u, FIFO Write Pointer: %u, Done Bytes: %u\n", + !!(status & SPI_BUSY), + (status >> SPI_FIFO_RD_PTR_SHIFT) & SPI_FIFO_RD_PTR_MASK, + (status >> SPI_FIFO_WR_PTR_SHIFT) & SPI_FIFO_WR_PTR_MASK, + (status >> SPI_DONE_BYTE_COUNT_SHIFT) & SPI_DONE_BYTE_COUNT_MASK); + + printk(BIOS_DEBUG, "CmdCode: %x\n", spi_read8(SPI_CMD_CODE)); addr = spi_get_bar() + SPI_FIFO; @@ -63,7 +74,6 @@ static void dump_state(enum spi_dump_state_phase phase) case SPI_DUMP_STATE_BEFORE_CMD: dump_size = spi_read8(SPI_TX_BYTE_COUNT); printk(BIOS_DEBUG, "TxByteCount: %x\n", dump_size); - printk(BIOS_DEBUG, "CmdCode: %x\n", spi_read8(SPI_CMD_CODE)); break; case SPI_DUMP_STATE_AFTER_CMD: dump_size = spi_read8(SPI_RX_BYTE_COUNT); |