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authorFelix Held <felix-coreboot@felixheld.de>2022-03-31 01:29:32 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-04-01 14:31:55 +0000
commite0c738c3df3b26fc5bedf8c876146cae150b5256 (patch)
tree6b0f5020d82544822ba80238bf4ab685dc71216e /src/soc/amd/common
parent3363db01735e9c9f59d19093a1e059139ae90d78 (diff)
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soc/amd/sabrina/i2c: handle all I2C pads as I23C pad type
Contradicting the PPR #57243 version 1.56, the I2C3 pad control register in the MISC ACPIMMIO region is the same new I23C pad type as the corresponding registers for I2C0..2 and not the older I2C pad control register type used on Picasso and Cezanne. All I2C pads being of the new I23C type is in line with the GPIOMUX settings for the pins used by I2C0..3 that can alternatively connect the pins to an I3C controller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I51b0ddf8ba2ccfee823e3d4d26a77b11825b1029 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63233 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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