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| author | Nico Huber <nico.h@gmx.de> | 2024-01-11 18:50:50 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-01-17 15:53:19 +0000 |
| commit | f55b711c07f6454c38a2de31c3eef5d489e639dd (patch) | |
| tree | 7f120c81a7d43659a8a24aadbecd952eb3c0335c /src/soc/amd/common | |
| parent | d5ed888367d7a59268327eba21642b25734df664 (diff) | |
| download | coreboot-f55b711c07f6454c38a2de31c3eef5d489e639dd.tar.gz coreboot-f55b711c07f6454c38a2de31c3eef5d489e639dd.tar.bz2 coreboot-f55b711c07f6454c38a2de31c3eef5d489e639dd.zip | |
tree: More use accessor functions for struct region fields
Always use the high-level API region_offset() and region_sz()
functions. This excludes the internal `region.c` code as well
as unit tests. FIT payload support was also skipped, as it
seems it never tried to use the API and would need a bigger
overhaul.
Change-Id: I18f1e37a06783aecde9024c15876b67bfeed70ee
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/amd/common')
| -rw-r--r-- | src/soc/amd/common/block/spi/fch_spi_ctrl.c | 4 | ||||
| -rw-r--r-- | src/soc/amd/common/psp_verstage/psp_verstage.c | 16 |
2 files changed, 12 insertions, 8 deletions
diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index b3d7c69a68a8..ec3eef6ba365 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -221,8 +221,8 @@ static int fch_spi_flash_protect(const struct spi_flash *flash, const struct reg size_t addr, len, gran_value, total_ranges, range; bool granularity_64k = true; /* assume 64k granularity */ - addr = region->offset; - len = region->size; + addr = region_offset(region); + len = region_sz(region); reg32 = pci_read_config32(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_START); rom_base = WORD_TO_DWORD_UPPER(reg32); diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 7d9ef35d5876..b49acae843ca 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -85,13 +85,17 @@ static uint32_t update_boot_region(struct vb2_context *ctx) if (vboot_is_firmware_slot_a(ctx)) { fname = "apu/amdfw_a"; - if (!fmap_locate_area("FW_MAIN_A", &fw_slot)) - map_base = rdev_mmap(boot_device_ro(), fw_slot.offset, fw_slot.size); + if (!fmap_locate_area("FW_MAIN_A", &fw_slot)) { + map_base = rdev_mmap(boot_device_ro(), + region_offset(&fw_slot), region_sz(&fw_slot)); + } } else { fname = "apu/amdfw_b"; - if (!fmap_locate_area("FW_MAIN_B", &fw_slot)) - map_base = rdev_mmap(boot_device_ro(), fw_slot.offset, fw_slot.size); + if (!fmap_locate_area("FW_MAIN_B", &fw_slot)) { + map_base = rdev_mmap(boot_device_ro(), + region_offset(&fw_slot), region_sz(&fw_slot)); + } } if (!map_base) { @@ -118,7 +122,7 @@ static uint32_t update_boot_region(struct vb2_context *ctx) psp_dir_addr = ef_table->new_psp_directory; bios_dir_addr = get_bios_dir_addr(ef_table); psp_dir_in_spi = (uint32_t *)((psp_dir_addr & SPI_ADDR_MASK) + - (uint32_t)map_base - fw_slot.offset); + (uint32_t)map_base - region_offset(&fw_slot)); if (*psp_dir_in_spi != PSP_COOKIE) { printk(BIOS_ERR, "PSP Directory address is not correct.\n"); cbfs_unmap(amdfw_location); @@ -129,7 +133,7 @@ static uint32_t update_boot_region(struct vb2_context *ctx) if (bios_dir_addr) { bios_dir_in_spi = (uint32_t *)((bios_dir_addr & SPI_ADDR_MASK) + - (uint32_t)map_base - fw_slot.offset); + (uint32_t)map_base - region_offset(&fw_slot)); if (*bios_dir_in_spi != BHD_COOKIE) { printk(BIOS_ERR, "BIOS Directory address is not correct.\n"); cbfs_unmap(amdfw_location); |