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| author | Varshit Pandya <pandyavarshit@gmail.com> | 2024-02-22 17:34:32 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-23 14:52:21 +0000 |
| commit | a138cfb422109018ba35c8f5d82621717eaf0611 (patch) | |
| tree | 52f00b790c8d282daf79b6a14c92373a68debeea /src/soc/amd/glinda/chip.h | |
| parent | 961ed9fe27108ef46fc6c0f2aad340bb02e09081 (diff) | |
| download | coreboot-a138cfb422109018ba35c8f5d82621717eaf0611.tar.gz coreboot-a138cfb422109018ba35c8f5d82621717eaf0611.tar.bz2 coreboot-a138cfb422109018ba35c8f5d82621717eaf0611.zip | |
soc/amd/glinda: Use pcie_gpp_dxio_update_clk_req_config
This function turns off gpp_clk for the devices which are disabled, and
adds the code to fix up the clock configuration depending on dxio
descriptors. Also this brings glinda in line with cezanne, mendocino,
phoenix and picasso. This also prepares glinda to use the common
function gpp_clk_setup_common.
Change-Id: Id66d1b7f0d8ec9a7cbd378ad6ad7d68eeab531f0
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80415
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/glinda/chip.h')
| -rw-r--r-- | src/soc/amd/glinda/chip.h | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/soc/amd/glinda/chip.h b/src/soc/amd/glinda/chip.h index d33261fa1900..085bac5d209e 100644 --- a/src/soc/amd/glinda/chip.h +++ b/src/soc/amd/glinda/chip.h @@ -7,6 +7,7 @@ #include <amdblocks/chip.h> #include <amdblocks/i2c.h> +#include <amdblocks/pci_clk_req.h> #include <gpio.h> #include <soc/i2c.h> #include <soc/southbridge.h> @@ -92,11 +93,7 @@ struct soc_amd_glinda_config { /* The array index is the general purpose PCIe clock output number. Values in here aren't the values written to the register to have the default to be always on. */ - enum { - GPP_CLK_ON, /* GPP clock always on; default */ - GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ - GPP_CLK_OFF, /* GPP clk off */ - } gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE]; + enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE]; /* performance policy for the PCIe links: power consumption vs. link speed */ enum { |