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| author | Jon Murphy <jpmurphy@google.com> | 2022-08-05 15:43:44 -0600 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-08-11 19:15:30 +0000 |
| commit | 4f732420526fdc1c969e910daca573dca72d7b82 (patch) | |
| tree | 26c74fa55c89edbdd7c36be5b966401910437694 /src/soc/amd/mendocino/include/soc/i2c.h | |
| parent | 251e26683e25fdbef329e9e731319ef95b0f7327 (diff) | |
| download | coreboot-4f732420526fdc1c969e910daca573dca72d7b82.tar.gz coreboot-4f732420526fdc1c969e910daca573dca72d7b82.tar.bz2 coreboot-4f732420526fdc1c969e910daca573dca72d7b82.zip | |
treewide: Rename Sabrina to Mendocino
'Mendocino' was an embargoed name and could previously not be used
in references to Skyrim. coreboot has references to sabrina both
in directory structure and in files. This will make life difficult
for people looking for Mendocino support in the long term. The code
name should be replaced with "mendocino".
BUG=b:239072117
TEST=Builds
Cq-Depend: chromium:3764023
Cq-Depend: chromium:3763392
Cq-Depend: chrome-internal:4876777
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/mendocino/include/soc/i2c.h')
| -rw-r--r-- | src/soc/amd/mendocino/include/soc/i2c.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/amd/mendocino/include/soc/i2c.h b/src/soc/amd/mendocino/include/soc/i2c.h new file mode 100644 index 000000000000..d06a92d5bc72 --- /dev/null +++ b/src/soc/amd/mendocino/include/soc/i2c.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_MENDOCINO_I2C_H +#define AMD_MENDOCINO_I2C_H + +#include <soc/gpio.h> +#include <types.h> + +#define GPIO_I2C0_SCL BIT(0) +#define GPIO_I2C1_SCL BIT(1) +#define GPIO_I2C2_SCL BIT(2) +#define GPIO_I2C3_SCL BIT(3) +#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + + +#define I2C0_SCL_PIN GPIO_145 +#define I2C1_SCL_PIN GPIO_147 +#define I2C2_SCL_PIN GPIO_113 +#define I2C3_SCL_PIN GPIO_19 + +#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx +#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx +#define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx +#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx + +void i2c_set_bar(unsigned int bus, uintptr_t bar); + +#endif /* AMD_MENDOCINO_I2C_H */ |