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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-09-20 18:51:27 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-09-21 18:26:12 +0000 |
| commit | 63e77b025251afba6202056f688854be38b6e28d (patch) | |
| tree | 8e14ce4c925f4ae77ff895f907437555d540c5fa /src/soc/amd/mendocino | |
| parent | 05a3c1de3816c9aecfb34e1273547d27a712c5e2 (diff) | |
| download | coreboot-63e77b025251afba6202056f688854be38b6e28d.tar.gz coreboot-63e77b025251afba6202056f688854be38b6e28d.tar.bz2 coreboot-63e77b025251afba6202056f688854be38b6e28d.zip | |
soc/amd/*/cpu: factor out common noncar mp_init_cpus
Since all non-CAR AMD SoCs have the same mp_init_cpus implementation,
factor it out and move it to a common location.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibf4fa667106769989c916d941addb1cba38b7f13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/mendocino')
| -rw-r--r-- | src/soc/amd/mendocino/cpu.c | 25 |
1 files changed, 0 insertions, 25 deletions
diff --git a/src/soc/amd/mendocino/cpu.c b/src/soc/amd/mendocino/cpu.c index 5d6bb169d713..842b04fb25ed 100644 --- a/src/soc/amd/mendocino/cpu.c +++ b/src/soc/amd/mendocino/cpu.c @@ -1,40 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpi.h> #include <amdblocks/cpu.h> -#include <amdblocks/iomap.h> #include <amdblocks/mca.h> -#include <console/console.h> #include <cpu/amd/microcode.h> #include <cpu/cpu.h> -#include <cpu/x86/mp.h> -#include <cpu/x86/mtrr.h> -#include <acpi/acpi.h> #include <device/device.h> #include <soc/cpu.h> -#include <soc/iomap.h> _Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of " "available cores, use the downcore_mode and disable_smt devicetree settings instead."); -/* MP and SMM loading initialization */ - -void mp_init_cpus(struct bus *cpu_bus) -{ - extern const struct mp_ops amd_mp_ops_with_smm; - if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS) - die_with_post_code(POSTCODE_HW_INIT_FAILURE, - "mp_init_with_smm failed. Halting.\n"); - - /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ - mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE, - FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT); - - /* SMMINFO only needs to be set up when booting from S5 */ - if (!acpi_is_wakeup_s3()) - apm_control(APM_CNT_SMMINFO); -} - static void zen_2_3_init(struct device *dev) { check_mca(); |