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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-07 03:08:27 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-08 20:15:09 +0000 |
| commit | 78633e3d810119b09653320e9ad43b07d569eada (patch) | |
| tree | 8f379905bc56f3ca2479dcbc324b58c3cbef9cf7 /src/soc/amd/mendocino | |
| parent | 9f5b2f75ad5c500dbe8a3d9f27e6107fd56ee76d (diff) | |
| download | coreboot-78633e3d810119b09653320e9ad43b07d569eada.tar.gz coreboot-78633e3d810119b09653320e9ad43b07d569eada.tar.bz2 coreboot-78633e3d810119b09653320e9ad43b07d569eada.zip | |
soc/amd/include/msr: factor out P state MSR enable bit to cpu/amd/msr.h
The bit position of the P state enable bit in the 8 P state MSRs is
identical for all AMD chips including the family 16h model 30h APU that
lives outside of soc/amd. The other bits in those 8 MSRs are more or
less family- and model-specific.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia69c33e28e2a91ff9a9bfe95859c1fd454921b77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/mendocino')
| -rw-r--r-- | src/soc/amd/mendocino/include/soc/msr.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/amd/mendocino/include/soc/msr.h b/src/soc/amd/mendocino/include/soc/msr.h index 4b2519569518..0fe4b6fcf062 100644 --- a/src/soc/amd/mendocino/include/soc/msr.h +++ b/src/soc/amd/mendocino/include/soc/msr.h @@ -4,8 +4,6 @@ #define AMD_MENDOCINO_MSR_H /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ -#define PSTATE_DEF_HI_ENABLE_SHIFT 31 -#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT) #define PSTATE_DEF_LO_CUR_DIV_SHIFT 30 #define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT) #define PSTATE_DEF_LO_CUR_VAL_SHIFT 22 |