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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-04 17:31:10 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-06 18:59:27 +0000 |
| commit | 2f5c7590770f7bbb00f899a1495675083872b0d7 (patch) | |
| tree | 50e46daaae55446be9dd84c8360c80b52d71d547 /src/soc/amd/picasso/Makefile.inc | |
| parent | 0a93f7a7e99bf0872e019adeed08bf7b620a8985 (diff) | |
| download | coreboot-2f5c7590770f7bbb00f899a1495675083872b0d7.tar.gz coreboot-2f5c7590770f7bbb00f899a1495675083872b0d7.tar.bz2 coreboot-2f5c7590770f7bbb00f899a1495675083872b0d7.zip | |
soc/amd: factor out common family 17h&19h TSC and monotonic timer code
The corresponding MSRs of all AMD family 17h and 19h CPUs/APUs match the
code.
Change-Id: I29cfef5d8920c29e36c55fc46a90eb579a042b64
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso/Makefile.inc')
| -rw-r--r-- | src/soc/amd/picasso/Makefile.inc | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index c77278337e03..d86d97e7e294 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_AMD_PICASSO),y) subdirs-y += ../../../cpu/amd/mtrr/ -subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/x86/mtrr @@ -17,8 +16,6 @@ bootblock-y += southbridge.c bootblock-y += i2c.c bootblock-y += uart.c bootblock-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c -bootblock-y += monotonic_timer.c -bootblock-y += tsc_freq.c bootblock-y += gpio.c bootblock-y += config.c bootblock-y += reset.c @@ -30,8 +27,6 @@ romstage-y += reset.c romstage-y += memmap.c romstage-y += uart.c romstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c -romstage-y += monotonic_timer.c -romstage-y += tsc_freq.c romstage-y += aoac.c romstage-y += southbridge.c romstage-y += psp.c @@ -44,8 +39,6 @@ verstage-y += aoac.c verstage_x86-y += gpio.c verstage_x86-y += uart.c verstage_x86-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c -verstage_x86-y += monotonic_timer.c -verstage_x86-y += tsc_freq.c verstage_x86-y += reset.c ramstage-y += i2c.c @@ -66,8 +59,6 @@ ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-y += uart.c ramstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c -ramstage-y += monotonic_timer.c -ramstage-y += tsc_freq.c ramstage-y += finalize.c ramstage-y += soc_util.c ramstage-y += psp.c @@ -80,8 +71,6 @@ ramstage-y += xhci.c ramstage-y += dmi.c smm-y += smihandler.c -smm-y += monotonic_timer.c -smm-y += tsc_freq.c ifeq ($(CONFIG_DEBUG_SMI),y) smm-y += uart.c smm-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c |