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authorRaul E Rangel <rrangel@chromium.org>2021-02-12 14:37:43 -0700
committerFelix Held <felix-coreboot@felixheld.de>2021-02-14 18:05:17 +0000
commit394c6b092251f0da8f0bd159e0eb08a41a6e4afc (patch)
treee9d347574e889fc911ebe512d2bfc012239a5d73 /src/soc/amd/picasso/Makefile.inc
parent844775059d8cb456dec988e6378f3a73ea730001 (diff)
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soc/amd: Move update_microcode.c to common/block/cpu
We also want to support uCode loading on cezanne. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6f10564c93ce72aea7ff52a8565d65d8b56452f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/picasso/Makefile.inc')
-rw-r--r--src/soc/amd/picasso/Makefile.inc1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index 99e2da104079..d2a5e4c3930a 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -48,7 +48,6 @@ ramstage-y += uart.c
ramstage-y += finalize.c
ramstage-y += soc_util.c
ramstage-y += fsp_params.c
-ramstage-y += update_microcode.c
ramstage-y += graphics.c
ramstage-y += pcie_gpp.c
ramstage-y += xhci.c