diff options
| author | Felix Held <felix.held@amd.corp-partner.google.com> | 2021-10-22 22:38:21 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-26 15:37:45 +0000 |
| commit | 3a79633920850cb1d44f515a9cfe8372c6c01341 (patch) | |
| tree | aef9b03b2e808647c97d8173d5d77cd1e7e6d334 /src/soc/amd/picasso/Makefile.inc | |
| parent | cb2fd20c7f5cf43776dddfe2dbafeb19475e81f3 (diff) | |
| download | coreboot-3a79633920850cb1d44f515a9cfe8372c6c01341.tar.gz coreboot-3a79633920850cb1d44f515a9cfe8372c6c01341.tar.bz2 coreboot-3a79633920850cb1d44f515a9cfe8372c6c01341.zip | |
soc/*/Makefile: don't add cpu/x86/cache
No SoC uses the ramstage-only x86_enable_cache helper function to call
enable_cache with some added port 0x80 and console output.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: I7c5039e1341fd4089078ad7ffb2fe6584a94045c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso/Makefile.inc')
| -rw-r--r-- | src/soc/amd/picasso/Makefile.inc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 5e0c318eb8e4..e3eab29e35de 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_AMD_PICASSO),y) subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/cache subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../common/psp_verstage |