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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-02-21 17:59:42 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-02-28 22:36:34 +0000 |
| commit | 54c80e1df16d356dc73030903daece5fcb50e7bc (patch) | |
| tree | f5bbe1e183ae867abb43a72b4519275f07420e7c /src/soc/amd/picasso/acpi.c | |
| parent | b6b5af11712b303dab085a5c7c11aa003d4842a8 (diff) | |
| download | coreboot-54c80e1df16d356dc73030903daece5fcb50e7bc.tar.gz coreboot-54c80e1df16d356dc73030903daece5fcb50e7bc.tar.bz2 coreboot-54c80e1df16d356dc73030903daece5fcb50e7bc.zip | |
soc/amd/*/acpi: add comment about p_lvl[2,3]_lat FADT field usage
The latency values in the _CST package override the values in the
p_lvl2_lat and p_lvl3_lat FADT fields. In Picasso, Cezanne, Mendocino,
Phoenix and Glinda generate_cpu_entries generates the _CST packages for
each CPU device. The coreboot code for Stoneyridge doesn't generate _CST
packages for the CPU objects, but those are provided via the PSTATE SSDT
binaryPI generates and agesa_write_acpi_tables gets and adds to the ACPI
tables. The AGESA reference code also sets those two FADT entries to the
equivalents of ACPI_FADT_C2_NOT_SUPPORTED and ACPI_FADT_C3_NOT_SUPPORTED
so this also matches the AGESA behavior.
From the ACPI 6.4 spec: "Values provided by the _CST object override
P_LVLx values in P_BLK and P_LVLx_LAT values in the FADT."
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1116a3013576b18b6f521604d6b0a9d75b971e0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/picasso/acpi.c')
| -rw-r--r-- | src/soc/amd/picasso/acpi.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 1d5a275d427e..f6fb9f259d34 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -82,6 +82,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fill_fadt_extended_pm_regs(fadt); + /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are + overridden by the _CST packages in the processor devices. */ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ |