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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-03 18:17:57 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-04 21:46:17 +0000 |
| commit | 88d8e2b74eb9b2b3186ccb519efd1dbd92a090cb (patch) | |
| tree | e12b8e1101702adbca28202d954310709f98beba /src/soc/amd/picasso/acpi/sb_fch.asl | |
| parent | ce66f34372bb9dcda107bae983d38da25a5664d1 (diff) | |
| download | coreboot-88d8e2b74eb9b2b3186ccb519efd1dbd92a090cb.tar.gz coreboot-88d8e2b74eb9b2b3186ccb519efd1dbd92a090cb.tar.bz2 coreboot-88d8e2b74eb9b2b3186ccb519efd1dbd92a090cb.zip | |
soc/amd/picassso/acpi: increase MMIO region size of GPIO controller
The GPIO controller on Picasso has 4 banks of GPIOs with a size of 256
bytes each, so increase the reserved size to match the hardware.
Also replace the base GPIO address with the corresponding define.
Change-Id: I453f1c531d612a0e82ee0d91762fec6cdb2b8556
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso/acpi/sb_fch.asl')
| -rw-r--r-- | src/soc/amd/picasso/acpi/sb_fch.asl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 6cbfc5f66432..c4dffed8afc9 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -34,7 +34,7 @@ Device (GPIO) ActiveLow, Exclusive, , , IRQR) { 0 } - Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400) } CreateDWordField (Local0, IRQR._INT, IRQN) If (PMOD) { @@ -44,7 +44,7 @@ Device (GPIO) } If (IRQN == 0x1f) { Return (ResourceTemplate() { - Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400) }) } Else { Return (Local0) |