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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-10 00:06:12 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-11 00:44:31 +0000 |
| commit | 8485637287a93095dc3d51725ad7be033af257cb (patch) | |
| tree | 9080fe7f0fe3b47be07bd294f44d5d4288bd4d9c /src/soc/amd/picasso/bootblock.c | |
| parent | d3e977112a6b07d372e36667dbe8f9c8fe5c30f7 (diff) | |
| download | coreboot-8485637287a93095dc3d51725ad7be033af257cb.tar.gz coreboot-8485637287a93095dc3d51725ad7be033af257cb.tar.bz2 coreboot-8485637287a93095dc3d51725ad7be033af257cb.zip | |
soc/amd/picasso: factor out write_resume_eip to common code
Change-Id: I24454aa9e2ccc98b2aceb6b189e072e6e50b8b30
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso/bootblock.c')
| -rw-r--r-- | src/soc/amd/picasso/bootblock.c | 22 |
1 files changed, 1 insertions, 21 deletions
diff --git a/src/soc/amd/picasso/bootblock.c b/src/soc/amd/picasso/bootblock.c index 0b52a173077e..7d1f01cec83e 100644 --- a/src/soc/amd/picasso/bootblock.c +++ b/src/soc/amd/picasso/bootblock.c @@ -2,12 +2,12 @@ #include <stdint.h> #include <symbols.h> +#include <amdblocks/cpu.h> #include <amdblocks/reset.h> #include <bootblock_common.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> -#include <cpu/amd/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/tsc.h> @@ -16,9 +16,6 @@ #include <soc/southbridge.h> #include <soc/i2c.h> #include <amdblocks/amd_pci_mmconf.h> -#include <acpi/acpi.h> - -asmlinkage void bootblock_resume_entry(void); /* PSP performs the memory training and setting up DRAM map prior to x86 cores being released. Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise, @@ -91,23 +88,6 @@ static void set_caching(void) enable_cache(); } -static void write_resume_eip(void) -{ - msr_t s3_resume_entry = { - .hi = (uint64_t)(uintptr_t)bootblock_resume_entry >> 32, - .lo = (uintptr_t)bootblock_resume_entry & 0xffffffff, - }; - - /* - * Writing to the EIP register can only be done once, otherwise a fault is triggered. - * When this register is written, it will trigger the microcode to stash the CPU state - * (crX , mtrrs, registers, etc) into the CC6 save area. On resume, the state will be - * restored and execution will continue at the EIP. - */ - if (!acpi_is_wakeup_s3()) - wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry); -} - asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { set_caching(); |