soc/amd/picasso/pci_devs: Update pci_devs.h with correct values

This is a squash of the following commits. The original values were
wrong, and had confusing naming.

soc/amd/picasso: Get rid of *_DEVID from pci_devs.h

Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Change-Id: I203449499840bf0a6df8bd879fb7d2e75a16b284
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153714

src/amd/picasso: Update PCI bridge devices

Orignal-Change-Id: I1fa9d52ce113eacdc5c9ba31ab46b6428a7d6ca9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>

Zork: Reorganizing ACPI and adding PCI bridge configs

Signed-off-by: Pranay Shoroff <pshoroff@google.com>
Original-Change-Id: I1e2095567525f302dfd0bce8e39001250523180b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2063536

soc/amd/picasso: Fix soc_acpi_name() to use devfn instead of devid

Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Change-Id: I2486e7e0059e0528f53d5a158c9328636563fe93
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153712

BUG=b:147042464
TEST=Build trembyle and boot to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I91bf7f9edcddf03027f8fdcaadf4e290ece10df5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

1 files changed, 52 insertions, 23 deletions

diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c
index 5c5b79d136a6..26dcbfb9df05 100644
--- a/src/soc/amd/picasso/chip.c
+++ b/src/soc/amd/picasso/chip.c
@@ -2,6 +2,7 @@
 
 #include <bootstate.h>
 #include <cpu/amd/mtrr.h>
+#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <drivers/i2c/designware/dw_i2c.h>
@@ -50,30 +51,58 @@ const char *soc_acpi_name(const struct device *dev)
 	if (dev->path.type != DEVICE_PATH_PCI)
 		return NULL;
 
-	switch (dev->path.pci.devfn) {
-	case PCIE0_DEVFN:
-		return "PBR4";
-	case PCIE1_DEVFN:
-		return "PBR5";
-	case PCIE2_DEVFN:
-		return "PBR6";
-	case PCIE3_DEVFN:
-		return "PBR7";
-	case PCIE4_DEVFN:
-		return "PBR8";
-	case HDA1_DEVFN:
-		return "AZHD";
-	case LPC_DEVFN:
-		return "LPCB";
-	case SMBUS_DEVFN:
-		return "SBUS";
-	case XHCI0_DEVFN:
-		return "XHC0";
-	case XHCI1_DEVFN:
-		return "XHC1";
-	default:
-		return NULL;
+	if (dev->bus->dev->path.type == DEVICE_PATH_DOMAIN) {
+		switch (dev->path.pci.devfn) {
+		case GNB_DEVFN:
+			return "GNB";
+		case IOMMU_DEVFN:
+			return "IOMM";
+		case PCIE_GPP_0_DEVFN:
+			return "PBR0";
+		case PCIE_GPP_1_DEVFN:
+			return "PBR1";
+		case PCIE_GPP_2_DEVFN:
+			return "PBR2";
+		case PCIE_GPP_3_DEVFN:
+			return "PBR3";
+		case PCIE_GPP_4_DEVFN:
+			return "PBR4";
+		case PCIE_GPP_5_DEVFN:
+			return "PBR5";
+		case PCIE_GPP_6_DEVFN:
+			return "PBR6";
+		case PCIE_GPP_A_DEVFN:
+			return "PBRA";
+		case PCIE_GPP_B_DEVFN:
+			return "PBRB";
+		case LPC_DEVFN:
+			return "LPCB";
+		case SMBUS_DEVFN:
+			return "SBUS";
+		default:
+			printk(BIOS_WARNING, "Unknown root PCI device: dev: %d, fn: %d\n",
+			       PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
+			return NULL;
+		}
+	}
+
+	if (dev->bus->dev->path.type == DEVICE_PATH_PCI
+	    && dev->bus->dev->path.pci.devfn == PCIE_GPP_A_DEVFN) {
+		switch (dev->path.pci.devfn) {
+		case XHCI0_DEVFN:
+			return "XHC0";
+		case XHCI1_DEVFN:
+			return "XHC1";
+		default:
+			printk(BIOS_WARNING, "Unknown Bus A PCI device: dev: %d, fn: %d\n",
+			       PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
+			return NULL;
+		}
 	}
+
+	printk(BIOS_WARNING, "Unknown PCI device: dev: %d, fn: %d\n",
+	       PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
+	return NULL;
 };
 
 struct device_operations pci_domain_ops = {