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| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2021-02-03 04:32:06 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-02-05 23:36:25 +0000 |
| commit | 68d68f1d7c7693f7e49634b6c2106d3c2630d4b0 (patch) | |
| tree | fd5100feff6968735ad41f803c2d6d7397904fb5 /src/soc/amd/picasso/chip.h | |
| parent | 4cecca49250e46375efbccf61e6085762c140c4c (diff) | |
| download | coreboot-68d68f1d7c7693f7e49634b6c2106d3c2630d4b0.tar.gz coreboot-68d68f1d7c7693f7e49634b6c2106d3c2630d4b0.tar.bz2 coreboot-68d68f1d7c7693f7e49634b6c2106d3c2630d4b0.zip | |
soc/amd/picasso: add UPD for RV2 USB3 phy setting adjust
add UPD for RV2 USB3 phy setting adjust.
Note: it only for RV2 silicon and not available for RV/PCO.
Usb 3.1 PHY Parameters:
1. RX_EQ_DELTA_IQ_OVRD_VAL
-Override value for rx_eq_delta_iq. Range 0-0xF
2. RX_EQ_DELTA_IQ_OVRD_EN
-Enable override value for rx_eq_delta_iq. Range 0-0x1
3. Override value for rx_vref_ctrl. Range 0 - 0x1F
4. Enable override value for rx_vref_ctrl. Range 0 - 0x1
5. Override value for tx_vboost_lvl: 0 - 0x7.
6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
7. Override value for rx_vref_ctrl. Range 0 - 0x1F
8. Enable override value for rx_vref_ctrl. Range 0 - 0x1
9. Override value for tx_vboost_lvl: 0 - 0x7.
10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
BUG=b:175192931
TEST=Build/verify the valule will been apply on dirinboz
Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/chip.h')
| -rw-r--r-- | src/soc/amd/picasso/chip.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 9a7d2a5bfc34..313b6c3abf5b 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -66,6 +66,13 @@ struct usb_pd_control { }; #define USB_PORT_COUNT 6 + +struct __packed usb3_phy_tune { + uint8_t rx_eq_delta_iq_ovrd_val; + uint8_t rx_eq_delta_iq_ovrd_en; +}; +/* the RV2 USB3 port count */ +#define RV2_USB3_PORT_COUNT 4 #define USB_PD_PORT_COUNT 2 enum sd_emmc_driver_strength { @@ -247,6 +254,30 @@ struct soc_amd_picasso_config { USB_OC_NONE = 0xf, } usb_port_overcurrent_pin[USB_PORT_COUNT]; + /* RV2 SOC Usb 3.1 PHY Parameters */ + uint8_t usb3_phy_override; + /* + * 1,RX_EQ_DELTA_IQ_OVRD_VAL- Override value for rx_eq_delta_iq. Range 0-0xF + * 2,RX_EQ_DELTA_IQ_OVRD_EN - Enable override value for rx_eq_delta_iq. Range 0-0x1 + */ + struct usb3_phy_tune usb3_phy_tune_params[RV2_USB3_PORT_COUNT]; + /* Override value for rx_vref_ctrl. Range 0 - 0x1F */ + uint8_t usb3_rx_vref_ctrl; + /* Enable override value for rx_vref_ctrl. Range 0 - 0x1 */ + uint8_t usb3_rx_vref_ctrl_en; + /* Override value for tx_vboost_lvl: 0 - 0x7. */ + uint8_t usb_3_tx_vboost_lvl; + /* Enable override value for tx_vboost_lvl. Range: 0 - 0x1 */ + uint8_t usb_3_tx_vboost_lvl_en; + /* Override value for rx_vref_ctrl. Range 0 - 0x1F.*/ + uint8_t usb_3_rx_vref_ctrl_x; + /* Enable override value for rx_vref_ctrl. Range 0 - 0x1. */ + uint8_t usb_3_rx_vref_ctrl_en_x; + /* Override value for tx_vboost_lvl: 0 - 0x7. */ + uint8_t usb_3_tx_vboost_lvl_x; + /* Enable override value for tx_vboost_lvl. Range: 0 - 0x1. */ + uint8_t usb_3_tx_vboost_lvl_en_x; + /* The array index is the general purpose PCIe clock output number. */ enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */ |