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| author | Kevin Chiu <Kevin.Chiu@quantatw.com> | 2020-09-18 17:30:30 +0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-09-20 17:24:40 +0000 |
| commit | cdd9f5cb72a7b119a384d0a1455c34e94efa89d2 (patch) | |
| tree | dba61903e4e0673955980122211fc53feb51b76d /src/soc/amd/picasso/chip.h | |
| parent | e0d749c23b604dd6dfb94d95a59e5db30900d0e7 (diff) | |
| download | coreboot-cdd9f5cb72a7b119a384d0a1455c34e94efa89d2.tar.gz coreboot-cdd9f5cb72a7b119a384d0a1455c34e94efa89d2.tar.bz2 coreboot-cdd9f5cb72a7b119a384d0a1455c34e94efa89d2.zip | |
soc/amd/picasso: Add THERMCTL_LIMIT DPTC parameter support
Add THERMCTL_LIMIT (die temperature limit) DPTC parameter
for clamshell/tablet mode.
BUG=b:157943445
BRANCH=zork
TEST=build
Change-Id: Id193a74210c92d1e45ed4824ee9c0fc9ceaa5e3a
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/picasso/chip.h')
| -rw-r--r-- | src/soc/amd/picasso/chip.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 11675097cf72..9c9ae7f7cd02 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -111,6 +111,7 @@ struct soc_amd_picasso_config { /* Lower die temperature limit */ uint32_t thermctl_limit; + uint32_t thermctl_limit_tablet_mode; /* FP5 Processor Voltage Supply PSI Currents. 0 indicates use SOC default */ uint32_t psi0_current_limit; |