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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-13 02:36:02 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-06-01 20:37:04 +0000 |
| commit | c4eb45fa85d9860ce94829c6c977b9e28a297bf9 (patch) | |
| tree | 4b1f29ce8cf52e878ee54e16127f685e53ac7f31 /src/soc/amd/picasso/chipset.cb | |
| parent | db4b21a1d04678041fae73be4a700f393cee879d (diff) | |
| download | coreboot-c4eb45fa85d9860ce94829c6c977b9e28a297bf9.tar.gz coreboot-c4eb45fa85d9860ce94829c6c977b9e28a297bf9.tar.bz2 coreboot-c4eb45fa85d9860ce94829c6c977b9e28a297bf9.zip | |
soc/amd/picasso: introduce and use chipset device tree
The chipset devicetree only has the essential PCIe devices enabled that
are needed for the SoC code to work. It also defines aliases for all
PCIe devices that can be used to reference the devices in the mainboard-
specific devicetrees and devicetree overrides. To make the change easier
to review that part will be done in a follow-up patch.
Despite missing in the PPR, device pci 18.7 exists on Picasso.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b7c3fd32579a23539594672593a243172c161c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/picasso/chipset.cb')
| -rw-r--r-- | src/soc/amd/picasso/chipset.cb | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/chipset.cb b/src/soc/amd/picasso/chipset.cb new file mode 100644 index 000000000000..906b18d0aa53 --- /dev/null +++ b/src/soc/amd/picasso/chipset.cb @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/amd/picasso + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 alias gnb on end + device pci 00.2 alias iommu off end + device pci 01.0 on end # Dummy Host Bridge, do not disable + device pci 01.1 alias gpp_bridge_0 off end + device pci 01.2 alias gpp_bridge_1 off end + device pci 01.3 alias gpp_bridge_2 off end + device pci 01.4 alias gpp_bridge_3 off end + device pci 01.5 alias gpp_bridge_4 off end + device pci 01.6 alias gpp_bridge_5 off end + device pci 01.7 alias gpp_bridge_6 off end + device pci 08.0 on end # Dummy Host Bridge, do not disable + device pci 08.1 alias internal_bridge_a off # internal bridge to bus A + device pci 0.0 alias gfx off end # internal GPU + device pci 0.1 alias gfx_hda off end # display HD Audio controller + device pci 0.2 alias crypto off end # cryptography coprocessor + device pci 0.3 alias xhci_0 off end + device pci 0.4 alias xhci_1 off end + device pci 0.5 alias acp off end # audio co-processor + device pci 0.6 alias hda off end # main HD Audio Controller + device pci 0.7 alias mp2 off end # sensor fusion hub (MP2) + end + device pci 08.2 alias internal_bridge_b off # internal bridge to bus B + device pci 0.0 alias sata off end + device pci 0.1 alias xgbe_0 off end + device pci 0.2 alias xgbe_1 off end + end + device pci 14.0 alias smbus on end # primary FCH function + device pci 14.3 alias lpc_bridge on end + device pci 14.6 alias sdhci off end + device pci 18.0 alias data_fabric_0 on end + device pci 18.1 alias data_fabric_1 on end + device pci 18.2 alias data_fabric_2 on end + device pci 18.3 alias data_fabric_3 on end + device pci 18.4 alias data_fabric_4 on end + device pci 18.5 alias data_fabric_5 on end + device pci 18.6 alias data_fabric_6 on end + device pci 18.7 alias data_fabric_7 on end + end +end |