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| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2020-08-03 22:36:13 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-08-05 14:45:37 +0000 |
| commit | e2497d0181f5ab20d012c761400601b15565ce58 (patch) | |
| tree | 776e14fa5926cd359a99268820cbe0d24088339d /src/soc/amd/picasso/cpu.c | |
| parent | b7184e28ba4d2155e07d7b51aa8a0a86095adb05 (diff) | |
| download | coreboot-e2497d0181f5ab20d012c761400601b15565ce58.tar.gz coreboot-e2497d0181f5ab20d012c761400601b15565ce58.tar.bz2 coreboot-e2497d0181f5ab20d012c761400601b15565ce58.zip | |
mb/google/zork: keep the c-state IO base address alignment
Align the C-state MSR value of BSP with AGESA.
BUG=b:162705221
BRANCH=none
TEST=Check the MSR value is correct and BSP can enter CC6 with AVT tool
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ib98d34af518439d338326446c20601867ad31690
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/picasso/cpu.c')
| -rw-r--r-- | src/soc/amd/picasso/cpu.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index c42f40036290..4d6e98d22144 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -46,6 +46,15 @@ int get_cpu_count(void) return 1 + (cpuid_ecx(0x80000008) & 0xff); } +static void set_cstate_io_addr(void) +{ + msr_t cst_addr; + + cst_addr.hi = 0; + cst_addr.lo = ACPI_CPU_CONTROL; + wrmsr(MSR_CSTATE_ADDRESS, cst_addr); +} + static void fill_in_relocation_params(struct smm_relocation_params *params) { uintptr_t tseg_base; @@ -109,6 +118,7 @@ static void model_17_init(struct device *dev) { check_mca(); setup_lapic(); + set_cstate_io_addr(); amd_update_microcode_from_cbfs(); } |