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| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2021-01-26 20:09:34 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-01-28 20:44:27 +0000 |
| commit | ad4f6d7c6e10027d420d3bae722b734674643873 (patch) | |
| tree | c019d327f3932e3dc30881e3ed9080c39799a31b /src/soc/amd/picasso/fch.c | |
| parent | 15e379aaf334e7931710b4208ccedf2f9ee44b0d (diff) | |
| download | coreboot-ad4f6d7c6e10027d420d3bae722b734674643873.tar.gz coreboot-ad4f6d7c6e10027d420d3bae722b734674643873.tar.bz2 coreboot-ad4f6d7c6e10027d420d3bae722b734674643873.zip | |
soc/amd/picasso: allow USB_PD port setting override
Allow to override the RFMUX setting if the board does not use PD chip.
BUG=b:177389383
BRANCH=none
TEST=Build; Check the USB_PD port been override.
Change-Id: Idd559b67668846805005a6e00f5a84655310f348
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49932
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/fch.c')
| -rw-r--r-- | src/soc/amd/picasso/fch.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 4fdaa391e79a..4db7a8c615bf 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -101,6 +101,22 @@ void sb_clk_output_48Mhz(void) misc_write32(MISC_CLK_CNTL1, ctrl); } +static void sb_rfmux_config_override(void) +{ + u8 port; + const struct soc_amd_picasso_config *cfg; + + cfg = config_of_soc(); + + for (port = 0; port < USB_PD_PORT_COUNT; port++) { + if (cfg->usb_pd_config_override[port].rfmux_override_en) { + write32((void *)(USB_PD_PORT_CONTROL + PD_PORT_MUX_OFFSET(port)), + cfg->usb_pd_config_override[port].rfmux_config + | USB_PD_RFMUX_OVERRIDE); + } + } +} + static void sb_init_acpi_ports(void) { u32 reg; @@ -218,6 +234,8 @@ void southbridge_init(void *chip_info) gpp_clk_setup(); sb_clk_output_48Mhz(); + + sb_rfmux_config_override(); } void southbridge_final(void *chip_info) |