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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-05-28 19:10:13 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-06-02 15:27:26 +0000 |
| commit | aea59401d053690ce06a5f89be272865e7905682 (patch) | |
| tree | 29cf83b6d5aa80c5ec247a084a2ee758c72428a7 /src/soc/amd/picasso/include/soc/iomap.h | |
| parent | 71971c9d7e3102f4568d24107dec9ac44277d073 (diff) | |
| download | coreboot-aea59401d053690ce06a5f89be272865e7905682.tar.gz coreboot-aea59401d053690ce06a5f89be272865e7905682.tar.bz2 coreboot-aea59401d053690ce06a5f89be272865e7905682.zip | |
soc/amd/picasso: remove warm reset flag code
Since the MCA(X) registers have defined values on the cold boot path,
the is_warm_reset check can be dropped. Also the warm reset bit in the
NCP_ERR register doesn't behave as the PPR [1] suggested; no matter if
something was written to the register or the machine went through a warm
reset cycle, the NCP_WARM_BOOT bit never got set.
[1] checked with PPR for AMD Family 17h Models 11h,18h B1 (RV,PCO)
#55570 Rev 3.15
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4e6df98ffd5d15ca204c9847a76c19c753726737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso/include/soc/iomap.h')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/iomap.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 5b75ecb4667a..b6f5dbb4076d 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -83,7 +83,6 @@ #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) /* 8 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ -#define NCP_ERR 0xf0 #define SMB_BASE_ADDR 0xb00 #define PM2_INDEX 0xcd0 #define PM2_DATA 0xcd1 |