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| author | Kangheui Won <khwon@chromium.org> | 2021-04-23 16:37:44 +1000 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-04-29 15:14:48 +0000 |
| commit | 3bad01373d771d9fce8ae7d667b2e3a3c2267d6d (patch) | |
| tree | b7a475695071a0a818d119a87220793f6723c8a7 /src/soc/amd/picasso/include | |
| parent | e71a6ee9a6092ca0611bf858c8145d94dc192e43 (diff) | |
| download | coreboot-3bad01373d771d9fce8ae7d667b2e3a3c2267d6d.tar.gz coreboot-3bad01373d771d9fce8ae7d667b2e3a3c2267d6d.tar.bz2 coreboot-3bad01373d771d9fce8ae7d667b2e3a3c2267d6d.zip | |
soc/amd/picasso: move PSP_SRAM addrs to separate header
These addresses will be changed in cezanne. Before start working on
cezanne, move these out to separate header as a clean-up.
TEST=emerge-zork coreboot
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I2499281d250aae701f86bfcc87c7681e5b684b6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/picasso/include')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/psp_verstage_addr.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/include/soc/psp_verstage_addr.h b/src/soc/amd/picasso/include/soc/psp_verstage_addr.h new file mode 100644 index 000000000000..61ae926bfdba --- /dev/null +++ b/src/soc/amd/picasso/include/soc/psp_verstage_addr.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_PICASSO_PSP_VERSTAGE_ADDR_H +#define AMD_PICASSO_PSP_VERSTAGE_ADDR_H + +/* + * Start of available space is 0x15000 and this is where the + * header for the user app (verstage) must be mapped. + * Size is 0x28000 bytes + */ +#define PSP_SRAM_START 0x15000 +#define PSP_SRAM_SIZE (160K) +#define VERSTAGE_START PSP_SRAM_START + +/* + * The temp stack can be made much smaller if needed - even 256 bytes + * should be sufficient. This is just for the function mapping the + * actual stack. + */ +#define PSP_VERSTAGE_TEMP_STACK_START 0x32000 +#define PSP_VERSTAGE_TEMP_STACK_SIZE (4K) + +/* + * The top of the stack must be 4k aligned, so set the bottom as 4k aligned + * and make the size a multiple of 4k + */ + +#define PSP_VERSTAGE_STACK_START 0x33000 +#define PSP_VERSTAGE_STACK_SIZE (40K) + +#endif /* AMD_PICASSO_PSP_VERSTAGE_ADDR_H */ |