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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2020-01-21 14:53:45 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-04-18 15:54:33 +0000 |
| commit | 901cb9ca46b334aeb0134fa19cc87b445420c7fa (patch) | |
| tree | 49041319f49b998515b6146286cf0780a5746b80 /src/soc/amd/picasso/memmap.c | |
| parent | 4fc59af03d0d76caa0b8497ea894f360c15c1a39 (diff) | |
| download | coreboot-901cb9ca46b334aeb0134fa19cc87b445420c7fa.tar.gz coreboot-901cb9ca46b334aeb0134fa19cc87b445420c7fa.tar.bz2 coreboot-901cb9ca46b334aeb0134fa19cc87b445420c7fa.zip | |
soc/amd/picasso: Move BERT region to cbmem
Allocate storage for the BERT reserved memory in cbmem, and add it in
response to a romstage hook. Add a Kconfig option for adjusting the
size reserved. This is different from the Stoney Ridge implementation
where it was intentionally oversized to ease MTRR use and to keep TSEG
aligned.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4759154d394a8f5b35c0ef0a15994bbef25492e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38694
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/memmap.c')
| -rw-r--r-- | src/soc/amd/picasso/memmap.c | 25 |
1 files changed, 2 insertions, 23 deletions
diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 0c8d9c0cdffd..c6fd11874abb 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -16,26 +16,6 @@ #include <soc/iomap.h> #include <amdblocks/acpimmio.h> -#if CONFIG(ACPI_BERT) - #if CONFIG_SMM_TSEG_SIZE == 0x0 - #define BERT_REGION_MAX_SIZE 0x100000 - #else - /* SMM_TSEG_SIZE must stay on a boundary appropriate for its granularity */ - #define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE - #endif -#else - #define BERT_REGION_MAX_SIZE 0 -#endif - -void bert_reserved_region(void **start, size_t *size) -{ - if (CONFIG(ACPI_BERT)) - *start = cbmem_top(); - else - start = NULL; - *size = BERT_REGION_MAX_SIZE; -} - void *cbmem_top_chipset(void) { msr_t tom = rdmsr(TOP_MEM); @@ -45,13 +25,12 @@ void *cbmem_top_chipset(void) /* 8MB alignment to keep MTRR usage low */ return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() - - CONFIG_SMM_TSEG_SIZE - - BERT_REGION_MAX_SIZE, 8*MiB); + - CONFIG_SMM_TSEG_SIZE, 8*MiB); } static uintptr_t smm_region_start(void) { - return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; + return (uintptr_t)cbmem_top(); } static size_t smm_region_size(void) |