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| author | Raul E Rangel <rrangel@chromium.org> | 2021-01-22 09:44:03 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-23 20:14:28 +0000 |
| commit | 91839eef5cb47ec82e9b9d824ac49d7edbff0534 (patch) | |
| tree | 06b7db931ce3045565d0678c6c78569100d1b628 /src/soc/amd/picasso/pcie_gpp.c | |
| parent | 76e72a0dd5b0dcc5c86a57545802e90e6c2a8d6b (diff) | |
| download | coreboot-91839eef5cb47ec82e9b9d824ac49d7edbff0534.tar.gz coreboot-91839eef5cb47ec82e9b9d824ac49d7edbff0534.tar.bz2 coreboot-91839eef5cb47ec82e9b9d824ac49d7edbff0534.zip | |
soc/amd/picasso/pcie_gpp: Add clarifying comment
Each bridge can only have one device.
BUG=b:170595019
BRANCH=zork
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7e476221dfcabc841cc1ed4bc4b1175c0652dcfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso/pcie_gpp.c')
| -rw-r--r-- | src/soc/amd/picasso/pcie_gpp.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index 8b6af4aa0f25..1acd021c9cd7 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -153,6 +153,7 @@ static void acpigen_write_PRT(const struct device *dev) irq_index = calculate_irq(pci_routing, i); acpigen_write_package(4); + /* There is only one device attached to the bridge */ acpigen_write_dword(0x0000FFFF); acpigen_write_byte(i); acpigen_write_byte(0); /* Source: GSI */ @@ -176,6 +177,7 @@ static void acpigen_write_PRT(const struct device *dev) link_template[8] = 'A' + (irq_index % 8); acpigen_write_package(4); + /* There is only one device attached to the bridge */ acpigen_write_dword(0x0000FFFF); acpigen_write_byte(i); acpigen_emit_namestring(link_template); |