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| author | Sean Rhodes <sean@starlabs.systems> | 2023-08-08 13:56:37 +0100 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2023-12-26 17:05:21 +0000 |
| commit | 06f4f65d241d1908c5d72cd0455351194ce52ca7 (patch) | |
| tree | a23cd1bc0e1d08b9b2c5beacd59bf931d431a91d /src/soc/amd/picasso/psp_verstage | |
| parent | b95ef282ff785f63ce2a74ff0140072856893687 (diff) | |
| download | coreboot-06f4f65d241d1908c5d72cd0455351194ce52ca7.tar.gz coreboot-06f4f65d241d1908c5d72cd0455351194ce52ca7.tar.bz2 coreboot-06f4f65d241d1908c5d72cd0455351194ce52ca7.zip | |
soc/intel/alderlake: Make C1e configurable
Make it possible to enable C1e from the devicetree by adding
`c1e_enable`. C1e was disabled by ea2a38be323173075db3b13729a4006ea1fef72d
for all RPL SOCs to reduce noise.
This will ensure that boards that disabled it based on CPUID are unchanged.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I758621393cb39345c2ba7b19a32872e84e1c5a19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77088
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/psp_verstage')
0 files changed, 0 insertions, 0 deletions