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| author | Martin Roth <martinroth@chromium.org> | 2020-07-09 15:55:15 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-07-10 15:38:53 +0000 |
| commit | 853c6237cbdf7c2642fc51af204f1666a57add3d (patch) | |
| tree | d6448f008340fc819b99ea31fe7b969ab4948d9b /src/soc/amd/picasso/psp_verstage | |
| parent | 3b5e196e6771a0a1722d82024816628662cbc99e (diff) | |
| download | coreboot-853c6237cbdf7c2642fc51af204f1666a57add3d.tar.gz coreboot-853c6237cbdf7c2642fc51af204f1666a57add3d.tar.bz2 coreboot-853c6237cbdf7c2642fc51af204f1666a57add3d.zip | |
soc/amd/picasso: Map AOAC registers to enable i2c after S3
When entering S3, zork shuts down the i2c controllers to save power.
On resume, we need to re-enable i2c before accessing them, so we need
to map the AOAC registers in verstage.
BUG=b:160834101
TEST=psp_verstage works after resume.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ia8aa4923898a50f2202b6ca8434cee61a5918e91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43333
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/psp_verstage')
| -rw-r--r-- | src/soc/amd/picasso/psp_verstage/fch.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index 9059c9e1609e..e01a684a341a 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -63,6 +63,11 @@ void io_write8(u16 reg, u8 value) write8((void *)(io_bar + reg), value); } +static void aoac_set_bar(void *bar) +{ + acpimmio_aoac = bar; +} + static struct { const char *name; struct { @@ -79,6 +84,7 @@ static struct { {"eSPI", {FCH_IO_DEVICE_ESPI}, espi_set_bar}, {"I2C2", {FCH_IO_DEVICE_I2C, 2}, i2c2_set_bar}, {"I2C3", {FCH_IO_DEVICE_I2C, 3}, i2c3_set_bar}, + {"AOAC", {FCH_IO_DEVICE_AOAC}, aoac_set_bar}, }; uintptr_t *map_spi_rom(void) |