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| author | Kangheui Won <khwon@chromium.org> | 2021-06-25 16:03:05 +1000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-21 16:53:17 +0000 |
| commit | ce0fad5e39c7d5b32ea39f2bb56b1f2b26de89f8 (patch) | |
| tree | e85f5103b76cbeb69fe3617bbba2f8c2aa00508a /src/soc/amd/picasso/psp_verstage | |
| parent | ce291b4327a888920fad453103094630ca247a57 (diff) | |
| download | coreboot-ce0fad5e39c7d5b32ea39f2bb56b1f2b26de89f8.tar.gz coreboot-ce0fad5e39c7d5b32ea39f2bb56b1f2b26de89f8.tar.bz2 coreboot-ce0fad5e39c7d5b32ea39f2bb56b1f2b26de89f8.zip | |
soc/amd/cezanne: enable crypto in psp_verstage
Enable RSA and SHA for cezanne since support has been added to the PSP.
Also picasso and cezanne have different enums definitions for
hash algorithm, so split that out into chipset.c.
BUG=b:187906425
TEST=boot guybrush, check cbmem -t and the logs
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I725b0cac801ac0429f362a83aa58a8b9de158550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/picasso/psp_verstage')
| -rw-r--r-- | src/soc/amd/picasso/psp_verstage/chipset.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/psp_verstage/chipset.c b/src/soc/amd/picasso/psp_verstage/chipset.c index b7acbcd2820a..83f956b236e6 100644 --- a/src/soc/amd/picasso/psp_verstage/chipset.c +++ b/src/soc/amd/picasso/psp_verstage/chipset.c @@ -23,3 +23,18 @@ uint32_t get_bios_dir_addr(struct psp_ef_table *ef_table) { return ef_table->bios1_entry; } + +int platform_set_sha_op(enum vb2_hash_algorithm hash_alg, + struct sha_generic_data *sha_op) +{ + if (hash_alg == VB2_HASH_SHA256) { + sha_op->SHAType = SHA_TYPE_256; + sha_op->DigestLen = 32; + } else if (hash_alg == VB2_HASH_SHA512) { + sha_op->SHAType = SHA_TYPE_512; + sha_op->DigestLen = 64; + } else { + return -1; + } + return 0; +} |