soc/amd/picasso: Remove all AGESA references

Family 17h will not use the Arch2008 (a.k.a. v5) wrapper.  Remove
all source, support functions, and comments related to AGESA.

Family 17h requires v9 which has no similarities to v5 for
integration into a host firmware.  AGESA v9 support will be added
via subsequent patches into the appropriate locations.

Change-Id: Iea1a41941a0ba364a6abaaf31cc8e1145db4a236
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 0 insertions, 117 deletions

diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 904f55620220..950b41f5a3d5 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -27,8 +27,6 @@
 #include <program_loading.h>
 #include <romstage_handoff.h>
 #include <elog.h>
-#include <amdblocks/agesawrapper.h>
-#include <amdblocks/agesawrapper_call.h>
 #include <soc/northbridge.h>
 #include <soc/romstage.h>
 #include <soc/southbridge.h>
@@ -40,22 +38,6 @@ void __weak mainboard_romstage_entry(int s3_resume)
 	/* By default, don't do anything */
 }
 
-static void agesa_call(void)
-{
-	post_code(0x37);
-	do_agesawrapper(AMD_INIT_RESET, "amdinitreset");
-
-	post_code(0x38);
-	/* APs will not exit amdinitearly */
-	do_agesawrapper(AMD_INIT_EARLY, "amdinitearly");
-}
-
-static void bsp_agesa_call(void)
-{
-	set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */
-	agesa_call();
-}
-
 asmlinkage void car_stage_entry(void)
 {
 	struct postcar_frame pcf;
@@ -63,58 +45,20 @@ asmlinkage void car_stage_entry(void)
 	void *smm_base;
 	size_t smm_size;
 	uintptr_t tseg_base;
-	msr_t base, mask;
-	msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
-	int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
 	int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();
-	int i;
 
 	console_init();
 
 	mainboard_romstage_entry(s3_resume);
 
-	bsp_agesa_call();
-
 	if (!s3_resume) {
 		post_code(0x40);
-		do_agesawrapper(AMD_INIT_POST, "amdinitpost");
-
-		post_code(0x41);
-		/*
-		 * TODO: This is a hack to work around current AGESA behavior.
-		 *       AGESA needs to change to reflect that coreboot owns
-		 *       the MTRRs.
-		 *
-		 * After setting up DRAM, AGESA also completes the configuration
-		 * of the MTRRs, setting regions to WB.  Anything written to
-		 * memory between now and and when CAR is dismantled will be
-		 * in cache and lost.  For now, set the regions UC to ensure
-		 * the writes get to DRAM.
-		 */
-		for (i = 0 ; i < vmtrrs ; i++) {
-			base = rdmsr(MTRR_PHYS_BASE(i));
-			mask = rdmsr(MTRR_PHYS_MASK(i));
-			if (!(mask.lo & MTRR_PHYS_MASK_VALID))
-				continue;
 
-			if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) {
-				base.lo &= ~0x7;
-				base.lo |= MTRR_TYPE_UNCACHEABLE;
-				wrmsr(MTRR_PHYS_BASE(i), base);
-			}
-		}
-		/* Disable WB from to region 4GB-TOM2. */
-		msr_t sys_cfg = rdmsr(SYSCFG_MSR);
-		sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB;
-		wrmsr(SYSCFG_MSR, sys_cfg);
 		if (CONFIG(ELOG_BOOT_COUNT))
 			boot_count_increment();
 	} else {
 		printk(BIOS_INFO, "S3 detected\n");
 		post_code(0x60);
-		do_agesawrapper(AMD_INIT_RESUME, "amdinitresume");
-
-		post_code(0x61);
 	}
 
 	post_code(0x43);
@@ -155,64 +99,3 @@ asmlinkage void car_stage_entry(void)
 
 	post_code(0x50);  /* Should never see this post code. */
 }
-
-void SetMemParams(AMD_POST_PARAMS *PostParams)
-{
-	const struct soc_amd_picasso_config *cfg;
-	const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
-
-	if (!dev || !dev->chip_info) {
-		printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n");
-		/* In case of a BIOS error, only attempt to set UMA. */
-		PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ?
-					UMA_AUTO : UMA_NONE;
-		return;
-	}
-
-	cfg = dev->chip_info;
-
-	PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset;
-
-	switch (cfg->uma_mode) {
-	case UMAMODE_NONE:
-		PostParams->MemConfig.UmaMode = UMA_NONE;
-		break;
-	case UMAMODE_SPECIFIED_SIZE:
-		PostParams->MemConfig.UmaMode = UMA_SPECIFIED;
-		/* 64 KiB blocks. */
-		PostParams->MemConfig.UmaSize = cfg->uma_size / (64 * KiB);
-		break;
-	case UMAMODE_AUTO_LEGACY:
-		PostParams->MemConfig.UmaMode = UMA_AUTO;
-		PostParams->MemConfig.UmaVersion = UMA_LEGACY;
-		break;
-	case UMAMODE_AUTO_NON_LEGACY:
-		PostParams->MemConfig.UmaMode = UMA_AUTO;
-		PostParams->MemConfig.UmaVersion = UMA_NON_LEGACY;
-		break;
-	}
-}
-
-void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly)
-{
-	const struct soc_amd_picasso_config *cfg;
-	const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
-	struct _PLATFORM_CONFIGURATION *platform;
-
-	if (!dev || !dev->chip_info) {
-		printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree"
-					" config, STAPM unchanged\n");
-		return;
-	}
-	cfg = dev->chip_info;
-	platform = &InitEarly->PlatformConfig;
-	if ((cfg->stapm_percent) && (cfg->stapm_time_ms) &&
-				    (cfg->stapm_power_mw)) {
-		platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent;
-		platform->PlatStapmConfig.CfgStapmTimeConstant =
-							cfg->stapm_time_ms;
-		platform->PkgPwrLimitDC = cfg->stapm_power_mw;
-		platform->PkgPwrLimitAC = cfg->stapm_power_mw;
-		platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled;
-	}
-}