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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-23 12:36:16 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-25 19:58:32 +0000 |
| commit | ec098b5e7f3546356bdd3a215711745c336bd3d8 (patch) | |
| tree | e2a8f05a7a401672eb3a2ddc337f88d94ff7e515 /src/soc/amd/picasso/romstage.c | |
| parent | 28e2353e07801e122da879a5848e5ce00af42824 (diff) | |
| download | coreboot-ec098b5e7f3546356bdd3a215711745c336bd3d8.tar.gz coreboot-ec098b5e7f3546356bdd3a215711745c336bd3d8.tar.bz2 coreboot-ec098b5e7f3546356bdd3a215711745c336bd3d8.zip | |
soc/amd: only print CPU family and model in bootblock
Printing this in both bootblock and romstage is redundant, since the CPU
family and model aren't expected to change between bootblock and
romstage entry.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Paul Menzel <pmenzel@molgen.mpg.de>
Change-Id: Id7c6aea0d8a6dac39114593584e534661faea89d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/picasso/romstage.c')
| -rw-r--r-- | src/soc/amd/picasso/romstage.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index aa8da1ea6976..c085a5355fd5 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -147,8 +147,6 @@ asmlinkage void car_stage_entry(void) console_init(); post_code(0x42); - u32 val = cpuid_eax(1); - printk(BIOS_DEBUG, "Family_Model: %08x\n", val); /* Snapshot chipset state prior to any FSP call. */ fill_chipset_state(); |