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authorChris Wang <chris.wang@amd.corp-partner.google.com>2020-02-14 18:24:54 +0800
committerFelix Held <felix-coreboot@felixheld.de>2020-05-18 19:28:08 +0000
commited03371e76239dae16b6397efef4814f8c30451e (patch)
tree54da98e758d1d6d89c569ba9187004c6db0923ac /src/soc/amd/picasso/romstage.c
parent15fd30f0407f64684c975405888534dbd4be5ebf (diff)
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soc/amd/picasso: add telemetry setting
Add telemetry setting for SDLE testing BUG=b:147570294 TEST=Build Morphius and check the setting was been applied Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If4bb75eeaaa68b2c5a6a36c28c34fb338be65851 Reviewed-on: https://chromium-review.googlesource.com/2056885 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Tested-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso/romstage.c')
-rw-r--r--src/soc/amd/picasso/romstage.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index f038456b2929..e6bc5c9c8fc4 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -74,6 +74,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mcfg->core_dldo_bypass = config->core_dldo_bypass;
mcfg->min_soc_vid_offset = config->min_soc_vid_offset;
mcfg->aclk_dpm0_freq_400MHz = config->aclk_dpm0_freq_400MHz;
+ mcfg->telemetry_vddcr_vdd_slope = config->telemetry_vddcr_vdd_slope;
+ mcfg->telemetry_vddcr_vdd_offset = config->telemetry_vddcr_vdd_offset;
+ mcfg->telemetry_vddcr_soc_slope = config->telemetry_vddcr_soc_slope;
+ mcfg->telemetry_vddcr_soc_offset = config->telemetry_vddcr_soc_offset;
}
asmlinkage void car_stage_entry(void)