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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-06-20 16:28:33 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-10-20 16:31:54 +0000 |
| commit | 39a4ac1502b658d4ef6b57c50a0e386eff91364a (patch) | |
| tree | 6c8fcc4f674d179a98eb5c8f9264d1446e8740e8 /src/soc/amd/picasso/smihandler.c | |
| parent | 06fd982030a9ec74c38a6a075e243ff9a931e0ed (diff) | |
| download | coreboot-39a4ac1502b658d4ef6b57c50a0e386eff91364a.tar.gz coreboot-39a4ac1502b658d4ef6b57c50a0e386eff91364a.tar.bz2 coreboot-39a4ac1502b658d4ef6b57c50a0e386eff91364a.zip | |
soc/amd/picasso: Update southbridge
Picasso's FCH has many similarities to Stoney Ridge, so few changes
are necessary. The most notable changes are:
* Update the index values for the C00/C01 interrupt routing
* FORCE_STPCLK_RETRY is not present
* PCIB is not defined
* FCH MISC Registers 0xfed80e00 numbering has changed
* C-state base moves from PM register to MSR
* Add option to determine the intended MUX settion for LPC vs. eMMC
* Remove the LEGACY_FREE option
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I69dfc4a875006639aa330385680d150331840e40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/picasso/smihandler.c')
| -rw-r--r-- | src/soc/amd/picasso/smihandler.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 9eddf853b632..4995acb484bd 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -163,7 +163,6 @@ static void sb_slp_typ_handler(void) /* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */ pci_ctrl = pm_read32(PM_PCI_CTRL); pci_ctrl &= ~FORCE_SLPSTATE_RETRY; - pci_ctrl |= FORCE_STPCLK_RETRY; pm_write32(PM_PCI_CTRL, pci_ctrl); /* Enable SlpTyp */ |