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| author | Furquan Shaikh <furquan@google.com> | 2020-04-28 18:57:52 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-04-30 21:00:06 +0000 |
| commit | 69c2811acc685f1d46aff081583af039388f7aab (patch) | |
| tree | 3b5074afe10f81f696738b0d39d064073ebdc396 /src/soc/amd/picasso/southbridge.c | |
| parent | 173c7c459473d35ff10c2d99daa54cec940402a8 (diff) | |
| download | coreboot-69c2811acc685f1d46aff081583af039388f7aab.tar.gz coreboot-69c2811acc685f1d46aff081583af039388f7aab.tar.bz2 coreboot-69c2811acc685f1d46aff081583af039388f7aab.zip | |
soc/amd/picasso: Allow mainboard to configure SPI settings
This change adds options to allow mainboard to configure SPI speed for
different modes as well as the SPI read mode.
BUG=b:153675510,b:147758054
BRANCH=trembyle-bringup
TEST=Verified that SPI settings are configured correctly for trembyle.
Change-Id: I24c27ec39101c7c07bedc27056f690cf2cc54951
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40421
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/southbridge.c')
| -rw-r--r-- | src/soc/amd/picasso/southbridge.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index c38f373a3619..4f25802141a1 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -23,6 +23,7 @@ #include <soc/pci_devs.h> #include <soc/nvs.h> #include <types.h> +#include "chip.h" #define FCH_AOAC_UART_FOR_CONSOLE \ (CONFIG_UART_FOR_CONSOLE == 0 ? FCH_AOAC_DEV_UART0 \ @@ -237,8 +238,11 @@ void sb_read_mode(u32 mode) static void sb_spi_config_modes(void) { - sb_set_spi100(SPI_SPEED_33M, SPI_SPEED_33M, - SPI_SPEED_16M, SPI_SPEED_16M); + const struct soc_amd_picasso_config *cfg = config_of_soc(); + + sb_read_mode(cfg->spi_read_mode); + sb_set_spi100(cfg->spi_normal_speed, cfg->spi_fast_speed, cfg->spi_altio_speed, + cfg->spi_tpm_speed); } static void sb_spi_init(void) |